Chips, and in particular memory chips, are manufactured and provided to purchasers with a guarantee that a chip will most likely operate without errors if operated within parameters specified by the manufacturer. That is to say, a chip may be designed to provide error-free data storage if the chip is within a certain age, temperature, voltage, clock frequency, refresh rate, or other similar error-sensitive operation factor. DRAM chips in particular are overdesigned so that every cell among the billions on a chip loses data only with a very low probability under normal operating conditions. However, almost all of the memory cells in a typical DRAM chip can hold their value even if the operating conditions are changed. If a DRAM chip is refreshed at a below-recommended rate, almost all of the cells in the chip will continue to accurately retain their assigned values. As a result, typical DRAM chips are consuming power in the form of refresh power that is unnecessary for their effective operation. FIG. 1 illustrates this concept.
FIG. 1 shows a graph 100. The graph 100 reflects expected error behavior for a chip over a range of values for an error-sensitive factor (ESF). Suppose, for example, that the ESF is temperature. Suppose also that when operated at a manufacturer's recommended power-related settings (e.g., voltage, refresh rate, etc.) the chip has a probability of error-free operation that varies as a function of the temperature, as represented by solid line 102. Note that at some ESF values the probability of error may be well below what is needed or practical use (e.g., failure might occur once in a hundred years of continuous operation). Suppose that a desired maximum probability of error is α. Note that at the manufacturer's specified power level, the probability of error will always be below α. However, if the chip is operated with less power, even though the probability of error generally increases, as shown by line 104, below some ESF values, the probability of error will be below α.
Not only are chips often over-provisioned with respect to current or actual conditions or ESF values, they may be over-provisioned for certain portions of a chip. Chip manufacturing is an intricate process with considerable intra-process variation. There are variations from chip to chip. Chip manufacturers set a threshold for rejecting chips that do not conform to a specified quality threshold (measured in terms of performance, errors-per-chip, etc.). However, such thresholds are usually set low to ensure adequate yields, especially for commodity chips like DRAM chips. As a result, there is considerable variation even among chips that pass quality control. Some chips may have areas or regions that are more error-tolerant than other regions and therefore may require less power.
Embodiments described herein relate to leveraging variations in chips for both power optimization and unique identification.